Modern electronic devices utilize semiconductor chips, commonly referred to as "integrated circuits" which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to hold a single chip and equipped with terminals for interconnection to external circuit elements. Such substrates may be secured to an external circuit board or chassis. Alternatively, in a so-called "hybrid circuit" one or more chips are mounted directly to a substrate forming a circuit panel arranged to interconnect the chips and the other circuit elements mounted to the substrate. In either case, the chip must be securely held on the substrate and must be provided with reliable electrical interconnection to the substrate. The interconnection between the chip itself and its supporting substrate is commonly referred to as "first level" assembly or chip interconnection, as distinguished from the interconnection between the substrate and the larger elements of the circuit, commonly referred to as a "second level" interconnection.
The structures utilized to provide the first level connection between the chip and the substrate must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as "input-output" or "I/O" connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial numbers of I/O connections.
The size of the chip and substrate assembly is a major concern. The size of each such assembly influences the size of the overall electronic device. More compact assemblies, with smaller distances between chips provide smaller signal transmission delays and hence permit faster operation of the device.
First level interconnection structures connecting a chip to a substrate ordinarily are subject to substantial strain caused by thermal cycling as temperatures within the device change during operation. The electrical power dissipated within the chip tends to heat the chip and substrate, so that the temperatures of the chip and substrate rise each time the device is turned on and fall each time the device is turned off. As the temperatures change, the chip and substrate may expand and contract by different amounts. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate. This relative movement deforms the electrical interconnections between the chip and substrate and places them under mechanical stress. These stresses are applied repeatedly with repeated operation of the device, and can cause breakage of the electrical interconnections.
Moreover, despite all of the efforts made during made during manufacture of the chips, some chips will be defective. These defects often cannot be detected until the chip is operated under power in a test fixture or in an actual assembly. A single bad chip can make a larger assembly including numerous chips and other valuable components worthless, or can require painstaking procedures to extricate the bad chip from the assembly. Therefore, the chips and the mounting components used in any chip assembly system should permit testing of chips and replacement of defective chips before the chips are fused to a substrate. The cost of the chip and substrate assembly is also a major concern.
Rai et al, U.S. Pat. No. 4,818,728 discloses a first substrate such as a chip with studs or bump leads protruding outwardly and a second substrate with recesses having solder for engaging the bump leads. Malhi et al, U.S. Pat. No. 5,006,792 discloses a test socket in which a substrate has an exterior ring-like structure and numerous cantilever beams protruding inwardly from the ring-like structure. Contacts are disposed on these cantilever beams so that the same can be resiliently engaged with contacts of a chip when the chip is placed in the socket. Nolan et al, A Tab Tape-Based Bare Chip Test and Bum Carrier, 1994 ITAP And Flip Chip Proceedings, pp. 173-179 discloses another socket with cantilevered contact fingers for engaging the contacts on a chip; in this case the contact fingers are formed on a flexible tab tape and reinforced by a silicone material so as to provide forcible engagement and a wiping action with the chip contact.
Hill et al, Mechanical Interconnection System For Solder Bump Dice, 1994 ITAP And Flip Chip Proceedings PP. 82-86, discloses a test socket for flip chip devices with solder bumps. The socket has rough, dendritic structures on contact pads; here again, the chip with the solder bumps thereon is forced into the engagement with the rough, dendritic structures so as to make temporary contact for testing.
The reference "MCM to Printed Wiring Board (Second Level) Connection Technology Options" by Alan D. Knight, (in Multichip Module Technologies and Alternatives, ed. by Daryl Ann Doane and Paul D. Franzon, Van Nostrand, 1993, pp. 504-509 and pp. 521-523), together with the corresponding U.S. Patent of Evans et al, U.S. Pat. No. 4,655,519 and Grabbe, U.S. Pat. No. 5,228,861 disclose additional connection systems using deformable contacts.
Despite all of these efforts in the art however, there have still been needs for improved components for connecting semiconductor chips and other microelectronic components; for improved methods for connecting such chips and components and for improved systems which include the connected chips and components.